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Contador ascendente y descendente en VHDL El siguiente contador tiene de salida 4 bits y cuanta en sentido ascendente y descendente con un control 'sentido'. Library IEEE.
When I compiled this program using ghdl it is showing error 'when' is expected instead of 'not'. Please help me to find the problem with this code.
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Shareefa FairooseShareefa Fairoose
1 Answer
you forgot these things:
![Vhdl Vhdl](/uploads/1/2/5/8/125825599/298181117.jpg)
![Flip Flip](http://centros.edu.xunta.es/iesmanuelchamosolamas/electricidade/fotos/contador_serie.gif)
1)
when '11' => not temp;
to when '11' => temp <= not temp;
2)
when others => temp <= 'X'
must have semicolon at the end when others => temp <='X';
3)you missed
end if
at the end of the if4)process sensitivity list contains a signal named ‘r’ which is undeclared
I’ve left out the signal j and k from the process because all the code you execute in the if statement is conditioned only by the clock, so there is no need to execute the process when j and k change their value and the clock isn’t on rising edge.
Andrea BellizziAndrea Bellizzi